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CDP1877,
CDP1877C
Programmable Interrupt Controller (PIC)
Features
Description
• Compatible with CDP1800 Series
The CDP1877 and CDP1877C are programmable 8-level interrupt control-lers designed for use in CDP1800 series microprocessor systems. They • Programmable Long Branch Vector Address and
provide added versatility by extending the number of permissible interrupts Vector Interval
When a high to low transition occurs on any of the PIC interrupt lines (IR0 to • 8 Levels of Interrupt Per Chip
IR7), it will be latched and, unless the request is masked, it will cause the • Easily Expandable
INTERRUPT line on the PIC and consequently the INTERRUPT input onthe CPU to go low.
• Latched Interrupt Requests
The CPU accesses the PIC by having interrupt vector register R(1) loaded • Hard Wired Interrupt Priorities
with the memory address of the PIC. After the interrupt S3 cycle, this regis-ter value will appear at the CPU address bus, causing the CPU to fetch an • Memory Mapped
instruction from the PIC. This fetch cycle clears the interrupt request latchbit to accept a new high-to-low transition, and also causes the PIC to issue a • Multiple Chip Select Inputs to Minimize Address
long branch instruction (CO) followed by the preprogrammed vector address Space Requirements
written into the PIC’s address registers, causing the CPU to branch to theaddress corresponding to the highest priority active interrupt request.
Ordering Information
If no other unmasked interrupts are pending, the INTERRUPT output of thePIC will return high. When an interrupt is requested on a masked interruptline, it will be latched but it will not cause the PIC INTERRUPT output to go low. All pending interrupts, masked and unmasked, will be indicated by a “1” in the corresponding bit of the status register. Reading of the status registerwill clear all pending interrupt request latches.
Several PICs can be cascaded together by connecting the INTERRUPT out-put of one chip to the CASCADE input of another. Each cascaded PIC pro-vides 8 additional interrupt levels to the system. The number of unitscascadable depends on the amount of memory space and the extent of theaddress decoding in the system.
Interrupts are prioritized in descending order; IR7 has the highest and IR0has the lowest priority.
The CDP1877 and CDP1877C are functionally identical. They differ in thatthe CDP1877 has a recommended operating voltage range of 4V to 10.5V,and the CDP1877C has a recommended operating voltage range of 4V to6.5V.
Programming Model
CDP1877, CDP1877C (PDIP)
PROGRAMMABLE INTERRUPT CONTROLLER (PIC)
CASCADE 1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 19994-82 CDP1877, CDP1877C
Absolute Maximum Ratings
Thermal Information
(All Voltages Referenced to VSS Terminal) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDP1877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1877C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oCLead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Static Electrical Specifications At T
CONDITIONS
CDP1877C
PARAMETER
1. Typical values are for TA = +25oC and nominal VDD.
2. IOL = IOH = 1µA3. Operating current is measured under worst-case conditions in a 3.2MHz CDP1802A system, one PIC access per instruction cycle.
CDP1877, CDP1877C
Operating Conditions At TA = Full package temperature range. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges: CDP1877C
PARAMETER
WRITE PAGE REGISTER
WRITE CONTROL REGISTER
WRITE MASK REGISTER
READ STATUS REGISTER
READ POLLING REGISTER
READ LONG BRANCH
REGISTER
REGISTER
REGISTER
PRIORITY
INTERRUPT
ENCODER/
INSTRUCTION
REGISTER
GENERATE
REGISTER
GENERATION
READ POLLING
REGISTER
INTERVAL
UPPER BITS
CONTROL REGISTER
CONTROL
REGISTER

FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1877
CDP1877, CDP1877C
Functional Definitions for CDP1877 and CDP1877C Terminals
TERMINAL
Data Bus - Communicates Information to and from CPU Chip Selects, Enable Chip if Valid during TPA Used as a Chip Select during TPA and as a Register Address During Read/Write Operations Used for Cascading Several PIC Units. The INTERRUPT Output from a Higher Priority PIC can be Tied to this Input, or the Input can be Tied to VDD if Cascading is Not Used.
PIC Programming Model
INTERNAL REGISTERS
Page Register
The PIC has three write-only programmable registers and This write only register contains the high order vector address the device will issue in response to an interruptrequest. This high-order address will be the same for any ofthe 8 possible interrupt requests; thus, interrupt vectoring dif-fers only in location within a specified page.
Control Register
The upper nibble of this write-only register contains the low interrupt request. The lower nibble is used for a master order vector address the device will issue in response to an interrupt reset, master mask reset and for interval select.
INTERVAL SELECT DETERMINESNUMBER OF BYTES ALLOCATED TOEACH INTERRUPT SERVICE ROUTINE INTERVAL
MASTER MASK RESET0 RESETS ALL MASK REGISTER BITS1 NO CHANGE MASTER INTERRUPT RESET0 RESETS ALL INTERRUPT LATCHES, CLEARS ANYPENDING INTERRUPTS1 NO CHANGE SETS UPPER BITS OF THE LOW ORDER VECTOR ADDRESS AS AFUNCTION OF THE INTERVAL SELECT CDP1877, CDP1877C
The Low Order Vector Address will be set according to the table below: LOW ADDRESS BITS
INTERVAL SELECTED NO. OF BYTES
2. All Don’t Care addresses and addresses A0-A3 are determined by interrupt request.
Mask Register
A ”1” written into any location in this write only register willmask the corresponding interrupt request line. All interruptinputs (except CASCADE) are maskable.
Status Register
In this read only register a “1” will be present in thecorresponding bit location for every masked or unmaskedpending interrupt.
Polling Register
This read only register provides the low order vector addressand is used to identify the source of interrupt if a pollingtechnique, rather than interrupt servicing, is used.
RESPONSE TO INTERRUPT (AFTER S3 CYCLE)
The PIC’s response to interrogation by the CPU is always 3bytes long, placed on the data bus in consecutive bytes inthe following format: First (Instruction) Byte:
CDP1877, CDP1877C
Second (High-Order Address) Byte
This byte is the High-Order vector Address that was writteninto the PIC’s Page Register by the user. The PIC does notalter this value in any way.
High-Order Vector Address
Third (Low-Order Address) Bytes
Indicates active interrupt input number (binary 0 to 7).
Bits indicated by AX (x = 4 to 7) are the same as pro-grammed into the control register. All other bits aregenerated by the PIC.
REGISTER ADDRESSES
In order to read/write or obtain an interrupt vector from anyPIC in the system, all chip selects (CS/AX, CS/AY, CS, CS)must be valid during TPA.
CS/AX and CS/AY are multiplexed addresses; both must behigh during TPA, and set according to this table during TPBto access the proper register.
ACTION TAKEN
READ Long Branch instruction and vector for highestpriority unmasked interrupt pending.
READ Polling Register (Used to identify INTERRUPTsource if Polling technique rather than INTERRUPT ser-vice is used.) CDP1877, CDP1877C
PIC Application Examples
Example 1 - Single PIC Application
Figure 2 shows all the connections required between CPUand PIC to handle eight levels of interrupt control.
FIGURE 2. PIC AND CPU CONNECTION DIAGRAM
Programming
Programming the PIC consists of the following steps: Values for Example 1 with LOCATION 84E0 arbitrarily cho-sen as the Vector Address with interval of eight bytes, IR4 2. Reset Master Interrupt Bit, B3, of Control Register.
In deriving the above addresses, all Don’t Care bits are 3. Write a “1” into the Interrupt Input bit location of the Mask 4. Write the High-Order Address byte into the Page When an INTERRUPT (IR4) is received by the CPU, it will address the PIC and will branch to the interrupt serviceroutine.
5. Write the Low-Order Address and the vector interval into The three bytes generated by the PIC will be: 6. Program R(1) of the CPU to point to the PIC so that the Long Branch instruction can be read from the PIC during TABLE 1. REGISTER ADDRESS VALUES
REGISTER
REGISTER ADDRESS
OPERATION
DATA BYTE
CDP1877, CDP1877C
Example 2 - Multi-PIC Application
Figure 3 shows all the connections required between CPUand PIC’s to handle sixteen levels of interrupt control.
HIGHEST
PRIORITY

INTERRUPT
CDP1877 IR6
PRIORITY
INTERRUPT
FIGURE 3. PICs AND CPU CONNECTION DIAGRAM
Register Address Assignments
• The 4-byte interval allows for a 3-byte long branch to any location in memory where the interrupt service routine is The low-byte register address for any WRITE or READ located. The branch can be preceded by a Save operation is the same as shown in Table 1.
Instruction to save previous contents of X and P on the The High-Byte register differs for each PIC because of the linear addressing technique shown in the example: • The 8-byte and 16-byte intervals allow enough space to perform a service routine without indirect vectoring. The amount of interval memory can be increased even further The R(1) vector address is unchanged. This address will if all 8 INTERRUPTS are not required. Thus a 4-level inter- select both PICs simultaneously (R(1). 1 = 111XXX00 = rupt system could use alternate IR Inputs, and expand the interval to 16 and 32 bytes, respectively.
H). Internal CDP1877 logic controls which PIC will respond when an interrupt request is serviced.
• The 4 Chip Selects allow one to conserve total allotted Additional PIC Application Comments
memory space to the PIC. For one chip, a total of 4address lines could be used to select the device, mapping The interval select options provide significant flexibility for it into as little as 4-K of memory space. Note that this selection technique is the only one that allows the PIC towork properly in the system: I/O mapping cannot be used • The 2-byte interval allows one to dedicate a full page to because the PIC must work within the CDP1800 interrupt interrupt servicing, with variable space between routines, structure to define the vector address. Decoded signals by specifying indirect vectoring with 2-byte short branch also will not work because the chip selects must be valid CDP1877, CDP1877C
Dynamic Electrical Specifications At T
5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 50pF CDP1877C
PARAMETER
MEMORY ADDRESS
HIGH BYTE
DATA FROM PIC TO BUS
VALID DATA
DATA FROM BUS TO PIC
VALID DATA
FIGURE 4. TIMING WAVEFORMS FOR CDP1877
CDP1877, CDP1877C
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurateand reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whichmay result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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